The The Merged Depletion Junction Field Effect Transistor or MFET was invented by me in 1975 while a doctoral student at Clemson University. The head of my doctoral committee was Professor Jay W. Lathrop, the co-inventor of photolithrography, who later worked with Jack Kilby, the inventor of the integrated circuit, at Texas Instruments before joining the faculty at Clemson University. At the end of my oral examination Professor Lathrop stated that the MFET could be the single most important advancement ever to come out of Clemson University. So far it has not. If you wish to know why read Part 1, the history of the development of the MFET.

For those not familiar with the design and operation of solid state devices, Part 2 covers the fundamentals of solid state devices at an introductory level.

To cut to the chase, Part 3 discusses scaling the MFET to today's 2 nanometer technology and the performance that would be expected at those dimensions. Included is a Grok-4 conversation where it is Grock using its knowledge of current and future semiconductor technologies to predict the performance of the MFET.

Part 4 Compares MFETs and CFETs of Part 3 to the Next Genertions of MOSFET Technologies. Again it is Grok's comparisons, not ours.

Part 5 Discusses the potential impact of the MFETs and CFETs of Part 3 on all aspects of semiconductor applications including Personal Computing, AI, Energy usage, and Bioengineering.

In 1975 as a Doctoral student at Clemson University I invented the The Merged Depletion Junction Field Effect Transistor or MFET. I was taking a course in solid state electronic devices being taught by Professor Jay W. Lathrop. We were learning about the Metal Oxide Field Effect Transistor (MOSFET) and its operating parameters and voltage limits. The MOSFET is a very simple three terminal device consisting of two PN junctions, the source and the drain, diffused into a substrate, the body, with a third terminal, the gate, covering the entire space between the source and drain insulated from the source, drain, and body by an insulating layer. It was here that I learned about merged depletion regions.

But inventing and deriving the simplified one dimensional equations was not enough. We had to prove it worked. There was one commercial 4000 series CMOS device whose structure was such that it could show the effect by overloading the input. The problem was that these devices had input protection circuits precisely prevent that. We tested over 1,000 devices from various manufacturers but only one showed an instantaneous hint that the MFET worked before it destroyed itsel. There was only one thing to do, build an MFET.

In 1975 Clemson was just starting to build up its semiconductor facilities and did not have the equipment to actually build semiconductor devices. As a result I took a leave of absence from Clemson to find a place where I could build one. Having an ongoing medical issue I moved to New York City where I stayed with my sister. While in New York I found out that Columbia University had the necessary diffusion furnaces but did not have any mask making equipment. Thinking I could find some other way to make the masks I enrolled at Columbia and signed up for a 2 credit hour lab session on semiconductors.

The first problem to solve was where to get the silicon wafers. To build an MFET at the large dimensions we were using, required very lightly doped wafers which were not available commercially at the time. Professor Lathrop was able to obtain 10 wafers from his contacts at Texas Instruments. But with only ten wafers the risk was too great that I would not be able to make a working device limited to only 10 attempts. I contacted several diamond cutters in New York's Diamond Center but not one of them would attempt cutting them. I was finally able to cut them using a diamond point engraving bit and a crude sliding jig. I now had over 100 partial wafers.

The next problen was making the photomasks. I made an 8 1/2 by 11 set of masks using Cut-and-strip masking film which I then photocopied each 25 times at the highest contrast setting to form my step and repeat full chip masks.

Still not a valid density comparison. Here is why. All FETs, MOSFETs, FinFets, GAAFets, JFETs, or MFETs have a source, channel, drain, and gate. To compare areas, we can define the length of all devices as the sum of the drain, source, channel, power, output, and isolation regions aligned with each other. The width of the device is the maximum width of each region including any isolation region while the length of the device is the sum of the lengths of all the regions. For a given actual minimum feature dimension a more valid comparison is to look at device orientation. For a horizontal device, MODFET, FINFET, GAA, and JFET, The length is the sum of the source, channel, drain, output region, output interconnect, and isolation region. For a vertical device the total length is the maximum length of the single longest region. This is how the true area comparison should be made. Try comparing the four horizontal devices named with the vertical MFET at 2nm assuming all could be manufactured to work at 2nm which they can't. We also know from our communication with Intel in 1982 that we first need to see if 45 years of semiconductor manufacturing improvements solves the variation in threshold voltage across a single chip.

For a valid Still not a valid density comparison. Here is why. All FETs, MOSFETs, FinFets, GAAFets, JFETs, or MFETs have a source, channel, drain, and gate. To compare areas, we can define the length of all devices as the sum of the drain, source, channel, power, output, and isolation regions aligned with each other. The width of the device is the maximum width of each region including any isolation region while the length of the device is the sum of the lengths of all the regions. For a given actual minimum feature dimension a more valid comparison is to look at device orientation. For a horizontal device, MODFET, FINFET, GAA, and JFET, The length is the sum of the source, channel, drain, output region, output interconnect, and isolation region. For a vertical device the total length is the maximum length of the single longest region. This is how the true area comparison should be made. Try comparing the four horizontal devices named with the vertical MFET at 2nm assuming all could be manufactured to work at 2nm which they can't. We will be using xAI's Grok-4 to obtain independent answer's to all questions